Part 12 -The 80GB Wall: GPU Infrastructure and Scheduling, Worked End to End
Last Updated on June 22, 2026 by Editorial Team
Author(s): Utkarsh Mittal
Originally published on Towards AI.
Our running example, fixed for the whole article
Part 11— https://pub.towardsai.com/ml-systems-design-series-retrieval-augmented-generation-rag-why-your-llm-doesnt-know-about-00e885bdbea9?source=friends_link&sk=55c086d99d3f6b7dfadd3d7c5226b4e0
The article walks through how GPU infrastructure, scheduling, and memory constraints determine the design of large-model training and inference systems. Starting from a real failure caused by spot capacity without checkpointing, it uses a fixed “Atlas-70B” example to compute the GPU memory bill (static weights, optimizer/Adam state, and activations), explains why gang scheduling and topology-aware allocation are essential, and shows how parallelism strategies (data parallelism vs. tensor/pipeline parallelism vs. ZeRO) are chosen based on what fits and how communication behaves. It then flips to inference, where constraints invert: MIG isolates memory slices for multi-tenant serving and dynamic batching improves utilization, while careful metric selection (MFU over raw “utilization”) prevents misleading performance assumptions. Finally, it covers spot preemption survival in detail—checkpoint sizing, storage-tier latency, checkpoint frequency tradeoffs, SIGTERM flushing, and a correct resume path—then concludes that everything is driven by an unavoidable starting number (1.12 TB) and that “memory math” is the key engineering skill as models outgrow single chips.
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